1. Field of the Invention
The present invention relates to a voltage generating (output) circuit used as a drive source of a device for directly or indirectly driving a capacitive load; a common electrode drive circuit of a display device provided with the voltage generating circuit, for driving a common electrode in a display device; and a signal line drive circuit and a gray-scale (gradation) voltage generating circuit of a display device provided with the voltage generating circuit, for driving the signal lines in a display device.
2. Description of the Related Art
An active matrix liquid crystal display device of FIG. 48 represents an example of the above-mentioned display device. This liquid crystal display device includes liquid crystal which is a display medium between two substrates 100 and 101 facing each other. Pixel electrodes 103 (P(i, j)) are arranged in a matrix on the liquid crystal side of the substrate 100, and signal lines (data lines or source lines) 104 (S(1), S(2), . . . , S(i), . . . , S(N)) and scanning lines (gate lines) 105 (G(1), G(2), . . . , G(j), . . . , G(M)) are provided at the periphery of each pixel electrode 103 so as to cross each other. A thin film transistor (TFT) 102 (T(i, j)) is provided as a switching element in the vicinity of each crossing portion of the signal lines 104 and the scanning lines 105. The TFT 102 is connected to the signal line 104, the scanning line 105, and the pixel electrode 103 so as to drive the pixel electrode 103.
A common electrode 101a is provided on the liquid crystal side of the other substrate 101. A capacitance of the liquid crystal contributing to a display is formed between the common electrode 101a and the pixel electrodes 103.
A source driver (signal line drive circuit) 200 is connected to the signal lines 104, and a gate driver 300 is connected to the scanning lines 105. The source driver 200 supplies a voltage to the signal lines 104; in the example shown in FIG. 48, a digital source driver to which a video signal is applied in a digital form is used. The source driver 200 and the gate driver 300 are provided with an output signal from a control circuit 600. The control circuit 600 supplies a control signal POL to a gray-scale voltage generating circuit 400 and a common electrode drive circuit 500. The gray-scale voltage generating circuit 400 outputs gray-scale voltages v0, v2, v2, and v3 to the source driver 200, and the common electrode drive circuit 500 outputs a common electrode voltage vcom to the common electrode 101a. 
Hereinafter, the gray-scale voltage generating circuit 400 and the common electrode drive circuit 500 provided in the display device thus constructed will be as described. FIG. 49 shows an example of a drive circuit as proposed in xe2x80x9cA driving circuit for a display devicexe2x80x9d, Japanese Laid-Open Patent Publication No. 5-53534 by H. Okada. This drive circuit works a s the gray-scale voltage generating circuit 400 as well as the common electrode drive circuit 500. The drive circuit is provided with an operational amplifier OPc for generating the common electrode voltage vcom, and operational amplifiers OP0 to OP3 for generating the gray-scale voltages v0 to v3. Each inversion input terminal of the operational amplifiers OPc, OP0, and OP1 is provided with the control signal POL. The control signal POL is inverted by an inverter INV and then input to each inversion input terminal of the operational amplifiers OP2 and OP3. Each non-inversion input terminal of the operational amplifiers OPc and OP0 to OP3 is provided with an output from resistance type potential dividers PDcom and PD0 to PD3, respectively. The resistance dividers PDcom and PD0 to PD3 respectively consist of two fixed resistors Rc1 and Rc2, R01 and R02, R11 and R12, R21 and R22, and R31 and R32. One terminal of each of the resistors Rc1, R01, R11, R21, and R31 is connected to a power supply Vdd at a positive electric potential; and each of the other terminals of the resistors Rc2, R02, R12, R22, and R32 is connected to a power supply Vss at a ground electric potential.
FIG. 50A shows an example of an output waveform of the above-mentioned drive circuit. When the control signal POL is at a high level, the common electrode voltage vcom and the gray-scale voltages v0 to v3 are output so that a voltage applied to a pixel has a positive polarity with respect to the common electrode (a time period in this state is referred to as xe2x80x9cpositive time periodxe2x80x9d). When the control signal POL is at a low level, the common electrode voltage vcom and the gray-scale voltages v0 to v3 are output so that a voltage applied to a pixel has a negative polarity with respect to the common electrode (a time period in this state is referred to as xe2x80x9cnegative time periodxe2x80x9d). In either time period, the absolute value of an electric potential difference between the common electrode and the pixel electrode is set to be higher in the same order of the data value 0 to 3 (i.e., |v0xe2x88x92vcom| less than |v1xe2x88x92vcom| less than |v2xe2x88x92vcom| less than |v3xe2x88x92vcom|).
The above relation represents a condition for driving a liquid crystal display body in a normally black mode. The above relation may be reversed when a liquid crystal display body is driven in a normally white mode. FIG. 50B shows an output in the case where the liquid crystal display body is driven in a normally white mode. It is not related to the present invention in which mode the liquid crystal display body is driven; therefore, in the following examples, either case (i.e., a normally black mode or a normally white mode) will be described. Unless otherwise stated, the level of a voltage refers to that in a positive time period. FIGS. 50A and 50B show waveforms in a line inversion in which the polarity of a voltage applied to a pixel is inverted per horizontal line (transverse line or row line).
The common electrode voltage vcom and gray-scale voltages v0 to v3 oscillate in synchronization with the control signal POL based on a reference voltage vM (i.e., a voltage applied to each non-inversion input terminal) are output from the operational amplifiers OPc and OP0 to OP3 by appropriately setting the fixed resistors R01, R02, R11, R12, R21, R22, R31, and R32. As is understood from FIG. 50A, the voltages vcom, v0, and v1 have a phase opposite to that of the voltages v2 and v3. The amplitude of these voltages are determined in terms of an amplification ratio of the operational amplifiers OPc and OP0 to OP3.
FIG. 51 shows the gray-scale voltages v0 to v3, based on the common electrode voltage vcom which is applied to the common electrode 101a. As is understood from FIG. 51, when a certain pixel is selected by the gate driver 300 through the scanning lines 105, the pixel electrode 103 is charged with an output (i.e., one of the gray-scale voltages v0 to v3) from the source driver 200 connected to the selected pixel, and the difference between the electric potential at the pixel electrode 103 and that of the common electrode 101a facing the pixel electrode 103 with the liquid crystal layer sandwiched therebetween.
As described above, in the case where the common electrode 101a is driven with an A.C. voltage, there is an advantage that the amplitude of a voltage to be applied to a signal line for obtaining a predetermined voltage between the pixel electrode 103 and the common electrode 101a can be decreased and a working voltage for the source driver 200 can be decreased (see Japanese Laid-Open Patent Publication No. 3-177890).
The gray-scale voltages v0 to v3 are supplied to the source driver 200 which is a signal line drive circuit.
FIG. 52 shows a circuit diagram showing the structure of the source driver 200. Video signal data is composed of two bits. That is, the video signal data has four values (0 to 3) and either of the gray-scale voltages v0 to v3 supplied from the gray-scale voltage generating circuit 400 shown in FIG. 48 is selected to be output in accordance with the respective value of the video signal data.
FIG. 53 shows a circuit diagram showing a circuit portion corresponding to the (i)th output. This circuit includes D-type flip-flops (sampling flip-flops) MSMP respectively for video signal data D0 and D1, flip-flops (holding flip-flops) MH respectively for the video signal data D0 and D1, a decoder DEC, analog switches ASW0 to ASW3 respectively provided between four kinds of power supplies V0 to V3 outputting gray-scale voltages v0 to v3, and a signal line S(i) ((i)th signal line 104). For sampling digital video signal data, various kinds of flip-flops other than D-type flip-flips can be used.
The operation of the source driver 200 with the above-mentioned structure will be described.
The two-bit video signal data (D0, D1) is taken in the sampling flip-flops MSMP at the time when a sampling pulse TSMPi corresponding to the (i)th signal line S(i) rises and held therein. When the sampling for one horizontal period is completed, an output pulse OE is given to the holding flip-flops MH and the video signal D0, D1 held in the sampling flip-flops MSMP are taken in the holding flip-flops MH to be output to the decoder DEC. The decoder DEC decodes the video signal data (D0, D1) and turns on one of the analog switches ASW0 to ASW3 in accordance with the values (0 to 3) of the video signal data. (D0, D1), whereby one of the four gray-scale voltages v0 to v3 is output to the signal line S(i).
FIG. 54 shows a liquid crystal display device which receives video signal data composed of three bits (D0, D1, D2). FIG. 55 partially shows a circuit corresponding to the signal line S(i) of the source driver 210 of FIG. 54. More specifically, the source driver 210 has this structure as many as the signal lines 104 of a display panel (i.e., the number of this structure owned by the source driver 210 is identical with that of the signal lines 104 of a display panel). In this case, the video signal data has 8 values (0 to 7), and the signal voltage given to each pixel is either of eight levels of gray-scale voltages v0 to v7 output from gray-scale power supplies V0 to V7 of the gray-scale voltage generating circuit 410.
The source driver 210 includes first-stage D-type flip-flops MSMP used for sampling data, second-stage D-type flip-flops MH for holding data, a decoder DEC, and a plurality of analog switches ASW0 to ASW7 respectively provided between the eight external power supplies V0 to V7 and the signal line S(i). The first-stage D-type flip-flops MSMP and the second-stage D-type flip-flops MH are provided for each bit (D0, D1, V2). Eight kinds of gray-scale voltages v0 to v7 from the gray-scale voltage generating circuit 410 and control signals S0 to S7 from the decoder DEC are respectively input to the analog switches ASW0 to ASW7. The respective analog switches ASW0 to ASW7 are turned on to output the gray-scale voltages v0 to v7 in accordance with the levels of the control signals S0 to S7.
In the case where the value of the video signal data is 3 in the source driver 210, the analog switch ASW3 turns a conductive state, and the gray-scale voltage v3 is output. In this case, the gray-scale voltage v3 drives the signal line S(i) through the analog switch ASW3. The gray-scale voltage generating circuit 410 is provided separately from the source driver 210 constituting a drive circuit; thus, the gray-scale voltages v0 to v7 are input to a drive circuit for each signal line S(i). The reason for this is that the number of the actual drive circuits is identical with that of the signal lines 104. For example, the number of the signal lines 104 is 1920 in the case of the VGA liquid crystal display device. There is a possibility that the gray-scale voltage generating circuit 410 drives all of the signal lines 104 simultaneously. In such a case, it is difficult to produce the gray-scale voltage generating circuit 410, which is capable of sufficiently supplying an electric current required for driving all of the signal lines 104 simultaneously, with high integration on the chip identical with that of the source driver 210.
In addition, the source driver 210 has problems such as a complicated structure and a large size. The reason for this is as follows: In the case where the digital video signal is 4 bit, 16 kinds of gray-scale voltages are required; as the video signal increases to 6 bit, 8 bit, etc., the number of gray-scale voltages required increases to 64, 256, etc. That is to say, the gray-scale voltages whose number is the same as that of the gray scales are required. Because of this, the structure of the power supply circuit for forming such a number of gray-scale voltages becomes complicated and is enlarged, and moreover, the connecting line between the voltage generating circuit and the analog switches becomes complicated.
In the above-mentioned situation, conventionally, the source driver 210 is only used for a 3-bit or 4-bit video signal. Thus, when a video signal is composed of a large number of bits, a drive circuit for performing a gray-scale display has been difficult to construct.
Considering the above, the inventors of the present invention achieved a method for interpolating a gray scale between a plurality of gray-scale voltages given from outside and have filed applications (Japanese Patent Application No. 4-129164 and Japanese Laid-open Patent Publication Nos. 4-136983, 4-140787 and 5-53534).
FIG. 24 shows a liquid crystal display device 220 having a basic structure of the present invention, based on an oscillating voltage driving method proposed in Japanese Laid-open Patent Publication No. 5-53534. FIG. 25 is a block diagram corresponding to the signal line S(i) of the source driver of FIG. 24 per output. The following description refers to FIGS. 24 to 27 to which examples of the present invention (described later) will also refer to.
The case where video signal data is composed of 3 bits (D0, D1, D2) will be described. More specifically, the video signal data has 8 values (i.e., 0 to 7), and a signal voltage to be applied to each pixel is either one of external gray-scale voltages v0, v2, v5, and v7 supplied from the gray-scale power supplies V0 to V7 of a gray-scale voltage generating circuit 420, or either one of or a plurality of external gray-scale voltages between any two of the external gray-scale voltages v0, v2, v5, and v7.
A source driver 220 is provided for each bit (D0, D1, D2) of the video signal data. The source driver 220 includes first-stage D-type flip-flops MSMP for sampling, second-stage D-type flip-flops MH for holding, a selection control circuit SCOL, and analog switches ASW0 to ASW7 provided between the external gray-scale voltage power supplies V0 to V7 and a signal line S(i). The external gray-scale voltages v0, v2, v5, and v7 and control signals S0, S2, S5, and S7 from the selection control circuit SCOL are input to the analog switches ASW0, ASW2, ASW5, and ASW7. Further, a signal t3 having a predetermined duty ratio is supplied to the selection control circuit SCOL.
The source driver 220 shown in FIGS. 24 and 25 has the same. effects as those of the source driver 210 shown in FIGS. 54 and 55 in terms of the realization of an 8-gray-scale display. In the source driver of FIG. 25, in order to realize the 8-gray-scale display, the number of external gray-scale power supplies is reduced to four (i.e., half of the conventional example shown in FIG. 55). In the source driver 220, the outputs from the gray-scale voltage power supplies V1, V3, V4, and V6 are formed by the above-mentioned oscillating voltage driving method.
Table 1 shows the relation between the video signal data input to the source driver 3 and the gray-scale voltage obtained from the source driver 3.
When the value of the video signal data is either of 1, 2, 5, or 7, one of the external gray-scale voltages v0 to v7 input from outside is output to the signal line S(i). When the value of the video signal data is other than 1, 2, 5, and 7, an oscillating voltage oscillating between any two external gray-scale voltages v0 to v7 are output to the signal line S(i). Thus, an 8-gray-scale display can be obtained from 4 external gray-scale voltages.
Hereinafter, the oscillating voltage driving method will be described.
The output waveform corresponding to the external gray-scale voltage v1 is shown in (1) of FIG. 26, and the output waveform corresponding to the external gray-scale voltages v0 and v2 are shown in (2) of FIG. 26. For example, an oscillating voltage oscillating a plurality of times between the external gray-scale voltages v0 and v2 during one output period (e.g., one horizontal scanning period) is output. The resistance and capacitance of wirings (i.e., signal line) between the source driver 220 and pixels forming a display panel constitutes a low pass filter (LPF), as shown in FIG. 56. The oscillating voltage passes through the LPF, whereby the gray-scale voltage v1 is applied to a pixel as an average value of the oscillating voltage.
FIG. 27 shows the waveform of the external gray-scale voltages v0 and v7 together with a common electrode signal vcom. FIG. 27 shows the waveforms in the case of line inversion in which the polarity of the voltage is inverted per horizontal scanning period. Hereinafter, the case of the line inversion will be described.
As is understood from FIG. 27, the external gray-scale voltage v0 has a polarity opposite to that of the common electrode signal vcom, and the external gray-scale voltage v0 and the common electrode signal vcom have rectangular waveforms which are alternately inverted at an identical point. In the case where the video signal data is 0, the capacitance of the liquid crystal layer of each pixel and the like is charged with a voltage between the gray-scale voltage v0 and the common electrode signal vcom.
As described above, the signal line 104 of the display panel is charged and discharged between a positive electric potential and a negative electric potential each time the outputs of the common electrode drive power supply 500 and the gray-scale generating circuit 420 have their polarity inverted. FIG. 56 shows an equivalent circuit in the case where the signal line 104 is considered as a load. In this equivalent circuit, an equivalent resistor Rs of the signal line 104 and an equivalent capacitance Cs thereof are connected in series. In a practical liquid crystal display device, the number of the signal lines 104 are 1920 (640xc3x973), for example, in a display panel with a VGA specification, and the gray-scale power supplies are in some cases required to drive a load 1920 times that of the circuit shown in FIG. 56.
Hereinafter, a peak electric current flowing when the polarity of the gray-scale voltage is inverted will be considered.
Assuming that the resistance of the equivalent resistor Rs of the signal line 104 is 50 Kxcexa9 and the maximum electric potential difference between the positive state and the negative state in the common electrode 101a is 10 V, the maximum peak electric current is 10/50 Kxcexa9xc3x971920=384 mA. Conventionally, the gray-scale power supply is required to have an ability of charging the maximum capacity of an electric current; therefore the gray-scale power supply may have a structure as shown in FIG. 57.
This circuit includes an operational amplifier OP and a complementary circuit (electric current amplifier) BUF. The operational amplifier OP is provided with a predetermined voltage and a control voltage POL. The output terminal of the operational amplifier OP is connected the complementary circuit BUF consisting of transistors Q1 and Q2. When an output voltage Vout from the complementary circuit BUF is fed back to the operational amplifier OP, the operational amplifier OP performs an inversion amplification. In the circuit of FIG. 57, the operational amplifier OP uses a slewing rate and an electric current capacity as large as possible.
The above-mentioned art causes the increase in cost. In addition, since the complementary circuit BUF (transistors Q1 and Q2) itself consumes an electric power, the consumption of electric current is increased. The increase in the consumption of electric current means an increase in electric current which is not required for driving the display panel.
There is no substantial difference between the case where the circuit shown in FIG. 57 is used as the common electrode drive circuit and the case where the circuit shown in FIG. 57 is used for each gray-scale voltage generating element of the gray-scale voltage generating circuit. However, in the case where the circuit shown in FIG. 57 is used for each gray-scale voltage generating element, the output voltage will have an amplitude and a center voltage corresponding to the respective data and will have the same phase with respect to the control voltage POL.
Further, there is another problem. That is, in the conventional gray-scale voltage generating device, when the signal line drive circuit (source driver) selects either of the gray-scale voltages v0 to v3, a load is rapidly fluctuated at the time of switching the polarity of the output of the gray-scale voltage generating circuit. In the case where the oscillating voltage driving method is applied to the signal line drive circuit, the load fluctuation is larger and the change speed thereof is higher than the case where a gray-scale voltage is merely selected.
Such a load fluctuation causes the fluctuation of the output voltage. FIG. 58 shows an example of an output waveform of a certain voltage level of the gray-scale voltage generating circuit, in the case where the oscillating voltage driving method is applied to the signal line drive circuit. As shown in this figure, since the voltage having the output waveform of the gray-scale voltage generating circuit is fluctuated, the voltage to be charged to a pixel is not uniform, resulting in the deterioration of display quality.
In order to solve the above-mentioned problems, it is considered that a capacitor be provided between the output terminal of the gray-scale voltage generating circuit and the gray-scale voltage input terminal of the signal line drive circuit, thereby absorbing and supplying a charge in accordance with the voltage fluctuation. However, in this case, it has been difficult to use a capacitor with a sufficient capacitance. The reasons for this are as follows:
When the output terminal of the gray-scale voltage generating circuit is connected to the capacitor, the capacitor itself becomes a load on the gray-scale voltage generating circuit performing an A.C. drive. This necessitates that the capacitor be charged and discharged by the gray-scale voltage generating circuit at the time of switching the polarity of the gray-scale voltage. As a result, there arises some problems such as the delayed output waveform of the gray-scale voltage generating circuit and the increased electric power consumption is increased. Thus, in actuality, it has been impossible to use a capacitor with a sufficient capacitance.
The above-mentioned problems are hardly ever known in the case where the source driver 210 having a structure shown in FIG. 55 is used; however, these problems are serious in the case of the signal line drive circuit using the oscillating voltage driving method as shown in FIG. 25. More specifically, a capacitor with a capacitance sufficient for compensating the current fluctuation due to the oscillating voltage which is switched at a higher speed per output period cannot be used. This causes the strain of the voltage as shown in FIG. 58 and in some cases, the deterioration of a display will be caused. In addition, in the common electrode driving circuit, the problems similar to those in the gray-scale voltage generating circuit arise. The voltage (output waveform) from the common electrode driving circuit is fluctuated because of the sudden load fluctuation of the source driver 220, in particular, using the oscillating voltage driving method; as a result, a display quality is deteriorated.
The drive circuit for a display device of this invention supplying a plurality of gray-scale voltages to the display device, based on externally supplied digital video signal data, comprises: a plurality of gray-scale power supplies, a plurality of drive power supplies, means for forming a first part of the plurality of gray-scale voltages using the gray-scale voltage power supplies, and means for forming a second part of the plurality of gray-scale voltages using the drive power supplies.
In one embodiment of the present invention, the gray-scale voltages formed by the drive power supplies is at least one of a maximum gray-scale voltage and a minimum gray-scale voltage among the plurality of gray-scale voltages.
In another embodiment of the present invention, the means for forming the second part of the plurality of gray-scale voltages by the drive power supplies comprises a pair of ON-OFF control means for forming one of the plurality of gray-scale voltages, respectively provided in first and second sections, one of the pair of ON-OFF control means in the first section is an AND circuit, the other of the pair of ON-OFF control means in the first section is a NOR circuit, the AND circuit performs an ON-OFF switch of one of the pair of ON-OFF control means in the second section, and the NOR circuit performs an ON-OFF switch of the other of the pair of ON-OFF control means in the second section.
According to another aspect of the present invention, a voltage generating circuit comprises:
two D.C. power supplies respectively outputting predetermined voltages at different levels;
means, which comprises switching means for alternately selecting the output voltages supplied from the two D.C. power supplies to output the selected voltage, for outputting an A.C. voltage based on the output voltage selected by the switching means; and
capacitor means branched to be connected to two wirings electrically connecting the respective D.C. power supplies to the switching means.
In one embodiment of the present invention, the capacitor means is independently connected to the two wirings.
In another embodiment of the present invention, the two wirings are connected to each other with the capacitor means therebetween.
In another embodiment of the present invention, two kinds of control voltages at predetermined electric potentials are respectively input to the two D.C. power supplies, one of the two D.C. power supplies outputs a voltage equal to a sum of the two kinds of control voltages, and the other of the two D.C. power supplies outputs a voltage equal to a difference between the two kinds of control voltages.
According to another aspect of the present invention, a common electrode drive circuit for a display device in which pixel electrodes are provided on one of two substrates facing each other with a display body sandwiched therebetween and a common electrode, which constitutes capacitance between the common electrode and the pixel electrodes, is provided on the other substrate, for driving the common electrode, comprises:
two D.C. power supplies respectively outputting predetermined voltages at different levels;
means, which comprises switching means for alternately selecting the output voltages supplied from the two D.C. power supplies to output the selected voltage, for outputting an A.C. voltage based on the output voltage selected by the switching means; and
capacitor means branched to be connected to two wirings electrically connecting the respective D.C. power supplies to the switching means.
In one embodiment of the present invention, the capacitor means is independently connected to the two wirings.
In another embodiment of the present invention, the two wirings are connected to each other with the capacitor means therebetween.
In another embodiment of the present invention, two kinds of control voltages at predetermined electric potentials are respectively input to the two D.C. power supplies, one of the two D.C. power supplies outputs a voltage equal to a sum of the two kinds of control voltages, and the other of the two D.C. power supplies outputs a voltage equal to a difference between the two kinds of control voltages.
According to another aspect of the present invention, a signal line drive circuit for a display device in which pixel electrodes and signal lines are provided on one of two substrates facing each other with a display body sandwiched therebetween, for supplying a signal to the pixel electrodes through the signal lines, comprises at least two voltage supply sources for supplying a voltage to the signal lines respectively comprising:
two D.C. power supplies respectively outputting predetermined voltages at different levels;
means, which comprises switching means for alternately selecting the output voltages supplied from the two D.C. power supplies to output the selected voltage, for outputting an A.C. voltage based on the output voltage selected by the switching means; and
capacitor means branched to be connected to two wirings electrically connecting the respective D.C. power supplies to the switching means.
In one embodiment of the present invention, the capacitor means is independently connected to the two wirings.
In one embodiment of the present invention, the two wirings are connected to each other with the capacitor means therebetween.
In one embodiment of the present invention, two kinds of control voltages at predetermined electric potentials are respectively input to the two D.C. power supplies, one of the two D.C. power supplies outputs a voltage equal to a sum of the two kinds of control voltages, and the other of the two D.C. power supplies outputs a voltage equal to a difference between the two kinds of control voltages.
According to another aspect of the present invention, a gray-scale voltage generating circuit for a display device in which pixel electrodes are provided on one of two substrates facing each other with a display body sandwiched therebetween, for supplying a plurality of gray-scale voltages to the pixel electrodes, based on a digital video signal externally supplied, comprises:
a plurality of voltage generating circuits outputting A.C. voltages at different levels; and
first capacitor means provided between any two of the plurality of voltage generating circuits,
each of the voltage generating circuits comprising:
two voltage sources outputting voltages at different levels; and
switching means which receives voltages output from the two voltage sources and externally outputs one of the voltages,
wherein one terminal of the first capacitor means is connected between either one of the two voltage sources and the switching means in one of the two of the voltage generating circuits and the other terminal of the first capacitor means is connected between either one of the two voltage sources and the switching means in the other of the two voltage generating circuits.
In one embodiment of the present invention, each of the voltage generating circuits further comprises second capacitor means, and one terminal of the second capacitor means is connected between one of the two voltage sources and the switching means.
In another embodiment of the present invention, the voltage generating circuit further comprises third capacitor means, one terminal of the third capacitor means is connected. between one of the two voltage sources and the switching means and the other terminal of the third capacitor means is connected between the other of the two voltage sources and the switching means.
According to another aspect of the present invention, a signal line drive circuit electrically connected to a capacitance load of a display body which performs a display with a charge charged in the capacitive load, comprises:
a gray-scale voltage generating circuit outputting a plurality of A.C. voltages at different levels; and
means for outputting a voltage to the display body, the voltage being among the plurality of A.C. voltages output from the gray-scale voltage generating circuit, corresponding to image data to be displayed on the display body,
each of the gray-scale voltage generating circuits comprising:
a plurality of voltage generating circuits outputting A.C. voltages at different levels; and
first capacitor means provided between any two of the plurality of voltage generating circuits,
each of the voltage generating circuit comprising:
two voltage sources outputting voltages at different levels; and
switching means which receives voltages output from the two voltage sources and outputs one of the two voltages to the capacitance load,
wherein one terminal of the first capacitor means is connected between either one of the two voltage sources and the switching means in one of the two voltage generating circuits and the other terminal of the first capacitor means is connected between either one of the two voltage sources and the switching means in the other of the two voltage generating circuits.
According to another aspect of the present invention, a voltage generating circuit comprises:
a power supply outputting a power supply signal in an A.C. waveform, the power supply signal alternately having a first period in which the power supply signal is at a first level and a second period in which the power supply signal is at a second level;
a power supply line one terminal of which is connected to the power supply;
a load connected to the other terminal of the power supply line, which receives the power supply signal from the power supply;
a plurality of charge storage means connected so as to be in parallel with the power supply line between the power supply and the load; and
a plurality of switching means respectively provided between the power supply line and each of the charge storage means, the plurality of switching means connecting a first part of the plurality of charge storage means to the power supply while disconnecting a second part of the plurality of charge storage means from the power supply when the power supply signal is in the first period, and connecting the second part of the plurality of charge storage means to the power supply while disconnecting the first part of the plurality of charge storage means from the power supply when the power supply signal is in the second period.
In one embodiment of the present invention, a pair of charge storage means are connected in parallel with the power supply line.
In another embodiment of the present invention, a pair of power supplies and a pair of power supply lines are used.
In another embodiment of the present invention, the plurality of switching means are respectively provided between one of the pair of charge storage means and the pair of power supply lines and between the other of the pair of charge storage means and the pair of power supply lines.
In another embodiment of the present invention, the power supply signal is in a rectangular waveform.
According to another aspect of the present invention, a voltage generating circuit comprises:
a power supply outputting a plurality of power supply signals in an A.C. waveform at different levels, each of the power supply signals alternately having a first period in which the power supply signal is at a first level and a second period in which the power supply signal is at a second level;
a plurality of power supply lines, one terminal of each of the power supply lines being connected to the power supply, respectively receiving the plurality of power supply signals from the power supply;
a plurality of loads, each of the loads being connected to the other terminal of each of the power supply lines, respectively receiving the plurality of power supply signals from the power supply;
charge storage means connected between the plurality of power supply lines provided between the power supply and the plurality of loads, having a first electrode and a second electrode;
a plurality of switching means respectively provided between the plurality of power supply lines and the first electrode of the charge storage means and between the plurality of power supply lines and the second electrode of the charge storage means, each of the plurality of switching means connecting the first electrode to a power supply line which receives one of the plurality of power supply signals while connecting the second electrode to a power supply line other than the power supply line which receives the one of the plurality of power supply signals, when the one of the plurality of power supply signals is in the first period, and each of the plurality of switching means connecting the first electrode to one of the power supply lines other than the power supply line which receives the one of the power supply signals while connecting the second electrode to the power supply line which receives the one of the power supply signals, when the one of the plurality of power supply signals is in the second period.
In one embodiment of the present invention, a pair of power supplies and a pair of power supply lines are used, a pair of charge storage means are connected in parallel with each of the power signal lines, the plurality of switching means comprise a first switching element, a second switching element, a third switching element, and a fourth switching element, the first and third switching elements are respectively provided between the first electrode and one of the pair of the power supply lines, the second and fourth switching elements are respectively provided between the second electrode and the other of the pair of the power supply lines, the first and fourth switching elements are synchronously turned on or off, and the second and third switching elements are coupled to each other.
In another embodiment of the present invention, the power supply signal is in a rectangular waveform.
According to another aspect of the present invention, a voltage generating circuit comprises:
a first power supply outputting a first voltage in an A.C. waveform oscillating between a first level and a second level to a power supply line connected to a load;
a second power supply outputting a second voltage at a predetermined level;
a third power supply outputting a third voltage at a predetermined level;
a first switch connected in parallel with the power supply line;
storage means connected between the first switch and the second power supply;
a second switch connected between the storage means and the third power supply so as to be in parallel with the first switch;
control means for controlling the first and second switches so that the second switch is in a non-conductive state when the first switch is in a conductive state, the second switch is in a conductive state when the first switch is in a non-conductive state, the storage means is disconnected from the third power supply by the second switch in a period including a period in which the storage means is connected to the first power supply by the first switch, and the storage means is connected to the third power supply by the second switch in a period including a period in which the storage means is disconnected from the first power supply by the first switch.
In one embodiment of the present invention, the control means selects a timing, at which the storage means is connected to the first power supply, right after the first voltage from the first power supply is switched between the first and second levels, and part of charge, which is to be supplied or absorbed between the first power supply and the load at a time of switching of a level of the first voltage, is compensated by the storage means.
In another embodiment of the present invention, a plurality of storage means are used, the control means connects the first part of the plurality of storage means to the first power supply only when the first voltage from the first power supply is at the first level and connects the second part of the plurality of storage means to the first power supply only when the first voltage from the first power supply is at the second level.
According to another aspect of the present invention, a voltage generating circuit comprises:
a first power supply outputting a first voltage in an A.C. waveform to a power supply line, the first voltage oscillating between a first level and a second level and having an output cut-off period between a period of the first level and a period of the second level;
a second power supply outputting a second voltage at a predetermined level;
a third power supply outputting a third voltage at a level in the vicinity of the first level;
a fourth power supply outputting a fourth voltage at a level in the vicinity of the second level;
a first switch and a second switch connected to the power supply line, the first switch being in parallel with the second switch;
first storage means connected between the first switch and the second power supply;
second storage means connected between the second switch and the second power supply;
a third switch connected between the first storage means and the third power supply so as to be in parallel with the first switch;
a fourth switch connected between the second storage means and the fourth power supply so as to be in parallel with the second switch; and
control means for controlling the first and third switches so that the third switch is in a non-conductive state when the first switch is in a conductive state, the third switch is in a conductive state when the first switch is in a non-conductive state, during a period including a period in which the first voltage output to the power supply line is at the first level, the storage means being disconnected from the third power supply by the third switch during a period in which the storage means is connected to the power supply line by the first switch, the storage means being connected to the third power supply by the third switch during a period in which the storage means is disconnected from the power supply line by the first switch, the storage means being connected to the power supply line during the output cut-off period of the first voltage,
the control means further controlling the second and fourth switches so that the fourth switch is in a non-conductive state when the second switch is in a conductive state, the fourth switch is in a conductive state when the second switch is in a non-conductive state, during a period including a period in which the first voltage output to the power supply is at the second level, the storage means being disconnected from the third power supply by the fourth switch during a period in which the storage means is connected to the power supply line by the second switch, the storage means being connected to the third power supply by the fourth switch during a period in which the storage means is disconnected from the power supply line by the second switch, the storage means being connected to the power supply line during the output cut-off period of the first voltage.
In one embodiment of the present invention, the first power supply comprises: a plurality of D.C. power supplies respectively outputting a plurality of D.C. voltages at different levels; a plurality of storage means respectively connected to an output terminal of each of the D.C. power supplies; and a plurality of switches respectively connected between the plurality of storage means and the power supply line.
In another embodiment of the present invention, the control means controls the first, second, third, and fourth switches so that the storage means is connected to the first power supply, at a time when the D.C. power supply, which has been connected to the storage means up to a time when the first voltage from the first power supply is switched between the first level and the second level, is disconnected therefrom or at a time right after the D.C. power supply is disconnected therefrom.
In another embodiment of the present invention, a D.C. power supply is used as the third and fourth power supplies.
According to another aspect of the present invention, a drive circuit for a display device in which pixel electrodes are provided on one of two substrates facing each other with a display body sandwiched therebetween and the common electrode forms capacitance between the common electrode and the pixel electrodes, comprises:
a common electrode drive circuit outputting two kinds of voltages at different levels in a rectangular waveform to the common electrode;
a voltage generating circuit generating a voltage at an arbitrary level between the levels of the two kinds of voltages in a rectangular waveform; and
switching means for switching an output of the common electrode drive circuit to an output of the voltage generating circuit during a predetermined period in which the level of the voltage in a rectangular waveform is switched.
In one embodiment of the present invention, the switching means includes a first switching element and a second switching element, the first switching element switches the output of the common electrode drive circuit or an output of a gray-scale voltage drive circuit, the second switching element switches the output of the voltage generating circuit, whereby the output of the common electrode drive circuit or the output of the gray-scale voltage drive circuit to the output of the voltage generating circuit during the predetermined period in which the level of the voltage in a rectangular waveform is switched, the first and second switching elements are controlled so as to be turned off together, and an OFF period is set to be longer than a switching period which is a transient period of the first and second switching elements.
According to another aspect of the present invention, a drive circuit for a display device comprises:
a gray-scale voltage drive circuit which directly outputs externally supplied gray-scale voltages or outputs interpolated voltages formed of the combination of the gray-scale voltages, thereby applying two kinds of voltages at different levels in a rectangular waveform to signal lines;
a voltage generating circuit generating a voltage at an arbitrary level between the levels of the two kinds of voltages in a rectangular waveform; and
switching means for switching an output of the gray-scale voltage drive circuit to an output of the voltage generating circuit during a predetermined period in which the level of the voltage in a rectangular waveform is switched.
In one embodiment of the present invention, the switching means includes a first switching element and a second switching element, the first switching element switches the output of the common electrode drive circuit or an output of a gray-scale voltage drive circuit, the second switching element switches the output of the voltage generating circuit, whereby the output of the common electrode drive circuit or the output of the gray-scale voltage drive circuit to the output of the voltage generating circuit during the predetermined period in which the level of the voltage in a rectangular waveform is switched, the first and second switching elements are controlled so as to be turned off together, and an OFF period is set to be longer than a switching period which is a transient period of the first and second switching elements.
According to another aspect of the present invention, a voltage generating circuit comprises:
a plurality of power supplies respectively outputting a voltage at a predetermined level, the respective levels of the voltages being different from each other;
a first switching means group including a plurality of switching means which respectively receive the voltage from the respective power supplies, in which the switching means is successively turned on, whereby a voltage whose level is switched from the level of the voltage from the respective power supplies is output; and
a second switching means one terminal of which is connected to an output side of the first switching means group and the other terminal of which is grounded, the second switching means being turned on only during a period including a time at which the level of the voltage, whose level is to be switched, is switched and being turned off during the other period.
In one embodiment of the present invention, either one of the plurality of switching means forming the first switching means group and the second switching means is selected to be turned on and switching means to be turned on is moved sequentially.
In another embodiment of the present invention, in the case where each of the switching means forming the first switching means group and the second switching means use a switch having a large transient response, an OFF period is set to be sufficiently long so that each switch is not turned on simultaneously.
According to another aspect of the present invention, a common electrode drive circuit for a display device in which pixel electrodes are provided on one of two substrates facing each other with a display body sandwiched therebetween and a common electrode, which constitutes capacitance between the common electrode and the pixel electrodes, is provided on the other substrate, for driving the common electrode, comprises:
a plurality of power supplies respectively outputting a voltage at a predetermined level, the respective levels of the voltages being different from each other;
a first switching means group including a plurality of switching means which respectively receive the voltage from the respective power supplies, in which the switching means is successively turned on, whereby a voltage whose level is switched from the level of the voltage from the respective power supplies is output; and
a second switching means one terminal of which is connected to an output side of the first switching means group and the other terminal of which is grounded, the second switching means being turned on only during a period including a time at which the level of the voltage, whose level is to be switched, is switched and being turned off during the other period.
In one embodiment of the present invention, either one of the plurality of switching means forming the first switching means group and the second switching means is selected to be turned on and switching means to be turned on is moved sequentially.
In another embodiment of the present invention, in the case where each of the switching means forming the first switching means group and the second switching means use a switch having a large transient response, an OFF period is set to be sufficiently long so that the switches are not turned on simultaneously.
According to another aspect of the present invention, a gray-scale voltage generating circuit for a display device in which pixel electrodes are provided on one of two substrates facing each other with a display body sandwiched therebetween, for supplying a plurality of gray-scale voltages to the pixel electrodes, based on an externally supplied digital video signal, comprises:
a plurality of power supplies respectively outputting a voltage at a predetermined level, the respective levels of the voltages being different from each other;
a first switching means group including a plurality of switching means which respectively receive the voltage from the respective power supplies, in which the switching means is successively turned on, whereby a voltage whose level is switched from the level of the voltage from the respective power supplies is output; and
a second switching means one terminal of which is connected to an output side of the first switching means group and the other terminal of which is grounded, the second switching means being turned on only during a period including a time at which the level of the voltage, whose level is to be switched, is switched and being turned off during the other period.
In one embodiment of the present invention, either one of the plurality of switching means forming the first switching means group and the second switching means is selected to be turned on and switching means to be turned on is moved sequentially.
In another embodiment of the present invention, in the case where each of the switching means forming the first switching means group and the second switching means use a switch having a large transient response, an OFF period is set to be sufficiently long so that the switches are not turned on simultaneously.
Thus, the invention described herein makes possible the advantages of (1) providing a drive circuit for a display device at a low cost in which the number of gray-scale voltage power supplies can be reduced; (2) providing a gray-scale voltage generating device, a signal line drive circuit, and a common electrode drive circuit which can sufficiently cope with the rapid fluctuation of a load and can realize a high-grade display; and (3) a gray-scale voltage generating device, a signal line drive circuit, and a common electrode drive circuit which makes possible a display device with low power consumption.